1. Field of the Invention
The disclosed invention relates to complementary metal oxide semiconductor (CMOS) integrated circuit structures, and is particularly directed to a latch-up resistant CMOS integrated circuit.
2. Description of Background Art
Monolithic CMOS integrated circuits are well known and include a plurality of N-channel and P-channel metal oxide semiconductor (MOS) transistors formed in a common silicon substrate. The major advantages of CMOS technology include low power dissipation, high noise immunity, a large supply voltage tolerance, symmetrical switching characteristics, and ease of circuit design. Despite such advantages, CMOS technology was not generally utilized until recently for very-large-scale-integration (VLSI) designs since the CMOS process technology is complex and expensive. However, with the continuous reduction in device (e.g. transistor) size and the advent of the VLSI era, CMOS technology has become a significant choice for VLSI designs, where perhaps the most important advantage of CMOS technology is low power consumption, since heat generation becomes a more significant factor as device density increases. Another advantage of CMOS technology is ease of circuit design.
As packing density increases in CMOS integrated circuits, a well-known phenomenon known as latch-up is more likely to occur. Latch-up occurs when a pair of parasitic bipolar transistors formed by adjacent N-channel and P-channel devices become uncontrollably conductive. Effectively, a silicon-controlled rectifier (SCR) is formed by the parasitic transistors and may be triggered, for example, by excessive input voltages.
The phenomenon of latch-up is analyzed in the articles "A Better Understanding of CMOS Latch-up," G.J. Hu, IEEE Transactions On Electron Devices, Vol. ED-31, No. 1, January 1984, pp. 62-67; and "Latchup Model for the Parasite p-n-p-n Path in Bulk CMOS," R. C. Fang and J. L. Moll, IEEE Transactions On Electron Devices, Vol. ED-31, No. 1, January 1984, pp. 113-120.
Present techniques for avoiding latch-up include the use of guard rings, which are heavily doped areas around each device. However, guard rings take up valuable chip area and thereby reduce packing density.
Another latch-up prevention structure is set forth in U.S. Pat. No. 4,172,767 issued on Nov. 6, 1979 to Stevenson and assigned to Hughes Aircraft Company. The Stevenson structure utilizes an additional region between complementary transistors, wherein the additional region is of a type opposite the type of the substrate material. Specifically, the additional region includes a heavily doped channel portion near the surface and lightly doped channel portion which extends downwardly from the heavily doped channel portion. However, it appears that the additional doped region would limit device packing density and would involve additional complex fabrication processes.
A presently proposed technique for latch-up prevention is the use of deep but narrow grooves to physically isolate the transistor devices. A depth of 5 to 7 micrometers is believed to be required while width should be maintained at 1 to 1.5 micrometers. This technique is discussed in an article "The Case for CMOS," R. D. Davies, IEEE Spectrum (October 1983), Vol. 20, No. 10, pp. 26-32. However, deep narrow groove isolation presents processing difficulties, which apparently have not yet been overcome. To the extent that narrow groove isolation may be capable of being achieved, it is believed that unacceptable structural instabilities may exist. Moreover, deep narrow groove isolation causes device sidewall leakages and limits utilization design flexibility. Further, while deep groove isolation reduces the probability of latch-up, it does not eliminate it. Deep narrow groove isolation has not been shown to be commercially practical.
The above-referenced Davies article also discusses a retrograde well, wherein the peak well-dopant concentration is below the substrate surface, as another proposed formation for helping to suppress latch-up. However, the article points out that the latch-up suppression of retrograding apparently has not been achieved in practice since a sufficiently small surface dopant concentration relative to the peak concentration has not yet been achieved.